module LED_Driver (
    input wire rst,
    input wire clk,
    input wire [11:0] addr,
    input wire wen,//CPU写地�?是写道dig的收，这个wen才会有效
    input wire [31:0] wdata,
    output reg [23:0] led
);



always@(posedge clk or posedge rst) begin
        if(rst) led <= 32'h00000000;
        else if (wen )led <= wdata[23:0];
        else led <= led;
    end

endmodule